The present invention relates to digital portable telephone sets and, more particularly, to digital portable telephone sets having a frequency deviation judging function.
FIG. 4 is a schematic a prior art example of digital portable telephone set. The illustrated digital portable telephone set comprises an antenna 101, a radio unit 102, a demodulating unit 103, an automatic frequency control unit (hereinafter referred to as AFC unit) 104, a clock generating unit (hereinafter referred to as CLK unit) 105, a voice processing unit 106, a reference oscillator 108, a control unit 109, an operating unit 110, a display unit 111, a microphone (MIC) 112 and a receiver (REC) 113.
In this digital portable telephone set, the radio unit 102 selects a signal frequency desired to be received from signal received by the antenna 101, and executes frequency conversion and amplification to provide an intermediate frequency signal (hereinafter referred to as IF signal) 161. The demodulator 103 demodulates the IF signal 161, and provides received data 162. The control unit 109 processes the received data 162, and provides a voice signal 163. The voice processing unit 106 converts the voice signal 163 to an analog signal to produce the voice through the receiver 113.
The voice processing unit 106 converts voice 165 inputted from the microphone 112 to a digital signal, and the control unit 109 processes this digital data to provide transmission data. The radio unit 102 modulates the transmission data to generate a carrier wave at a prescribed frequency, and amplifies the generated carrier wave. The amplified carrier wave is transmitted from the antenna 101.
The operating unit 110 is provided for inputting telephone number and other data, and it transfers the input data to the control unit 109. The display unit 111 displays various items. The CLK unit 105 generates a clock for timing processing, time instant display and so forth. The reference oscillator 108 generates a reference frequency used in a frequency generating unit in the radio unit 102 and an exact frequency used in the control unit 109 and the demodulating unit 103. The AFC unit 104 controls the reference oscillator 108 to obtain a frequency thereof identical with the exact frequency of the base station, which the signal is received from.
The demodulating unit 103 will now be described. The digital portable telephone system adopts π/4 shift DQPSK (Differential Quadrature Phase Shift Keying) as modulating system. As this demodulating system, an example of demodulating circuit in a delay detection system, which is usually used in the digital portable telephone set, is shown in FIG. 5. FIG. 5 is a block diagram showing the example of the demodulating circuit in the delay detection system. This demodulating circuit is well known, and is not described in detail here.
Referring to FIG. 5, the demodulating unit 103 includes a phase detecting unit 121, a data (DATA) reproducing unit 122, a phase correcting unit 123, a clock reproducing unit (hereinafter referred to as CLK reproducing unit) 124 and a demodulating clock unit 125.
The phase detecting unit 121 provides an IF (intermediate frequency) signal from the radio unit 102 as phase data 129 under control of a clock of the reference frequency (or instance 14.4 MHz) 128 at a timing of symbol clock 132. The data reproducing unit 122 produces received data 133 from the phase data 129, and provides the generated received data 133.
The phase correcting unit 123 corrects the phase of the phase data 129, and provides a phase-corrected IF signal 130, which is used in the AFC unit 104. The demodulating CLK unit 125 has a PLL (Phase-Locked Loop) circuit construction, and provides a demodulating clock 181 (at 2.688 MHz, for instance) by using the reference frequency 128. The CLK reproducing unit 124 divides the frequency of the demodulating clock 181 to 1/128 to provide symbol clock 132 (at 21 kHz, for instance) and also to 1/64 to provide data clock (at 42 kHz, for instance). Also, according to the difference between the phase shits in the first and second symbol intervals of the phase data 129, the unit 123 adjusts the phase timing of the symbol and data clocks 132 and 131 to be coincident with the symbol timing of the IF signal 127.
Features of the data reproducing unit 122 will now be described. FIG. 6 is a block diagram showing a first prior art example of data detecting circuit 122 used in a prior art delay detecting circuit. This prior art example is disclosed in detail in Japanese Patent Laid-Open No. 3-188737, and it is not described here in detail.
A one symbol delaying unit 141 delays the phase data 129 from the phase detecting unit 121 by one symbol. A subtracter 142 subtracts delayed phase-data 151 obtained by one symbol delaying and the phase data 129 from each other, and provides the difference as 5-bit phase difference data. A decoder 143 decodes the phase difference data 152, and converts the upper two bits and lower three bits of the result of decoding to received data 133a and quality data 133b, respectively. The received data 133a and quality data 133b are fed put as demodulation data 133 to the control unit 109.
Of the demodulation data 133, the quality data 133b is computationally processed in the control unit 109 for being used as frequency deviation detecting means. When the frequency deviation exceeds a predetermined value, the control unit 109 operates the AFC unit 104. The control unit 109 further computationally processes the quality data 133b to generate quality data of the receiving line. The quality data is used as data means for line control in the portable telephone system.
However, the first prior art example of data reproducing unit 122 used in the prior art delay detecting circuit, has a drawback that even a slight deviation of the received frequency results in receiving sensitivity deterioration and error factor deterioration. To cope with this drawback, a second prior art example of data reproducing unit 122 as shown in FIG. 7 is sometimes used. FIG. 7 is a block diagram showing the second prior art example of data reproducing unit 122.
The second prior art example of data reproducing unit 122 shown in FIG. 7 has a feature that it can obtain good received frequency and is free from error factor deterioration irrespective of received frequency deviation. The principles underlying this second prior art example are described in detail in Japanese Patent Laid-Open No. 57-164645, and are not described here. The circuit construction of this example is described in detail in Japanese Patent Laid-Open No. 7-183927 and Japanese Patent Laid-Open No. 6-205062, and is not described in detail here.
The difference of the second prior art example shown in FIG. 7 from the first prior art example shown in FIG. 6 is as follows. In the prior art example 2, a correcting circuit 144 receives lower three bits (corresponding to quality data 133b) of phase difference data 152 provided from a subtracter 142, and calculates a phase difference due to the frequency deviation. The circuit 144 feeds the phase difference thus obtained as correcting value 153 back to the subtracter 142. On the other hand, in the first prior art example, no such process as feeding out lower three bits of the phase difference data 152 to the correcting circuit 144 is executed.
FIG. 8 shows the construction of the correcting circuit 144 in the data reproducing unit 122. Referring to the Figure, the correcting circuit 144 includes an accumulating unit 148 and an average calculating unit 149. The accumulating unit 148 accumulates lower three bits of the phase difference data 152 a number of symbol times, and feeds out the result of accumulation to the average-calculating unit 149. The average calculating unit 149 calculates average data in a fixed symbol times number section, thereby feeding out the correcting value 153 to the subtracter 142.
However, the second prior art example of data reproducing unit 122 has a drawback that it is incapable of computing the frequency deviation from the quality data 133b outputted from the decoder 143. In other words, although this example has an advantageous feature that frequency deviation does not result in the received frequency deterioration or error factor deterioration, because the numerical value of the quality data 133b is not changed irrespective of frequency deviation, the control unit 109 can not detect frequency deviation by computing the quality data 133b. Consequently, the AFC unit 104 can not be started despite the fact that the frequency is deviated.
In the mean item, techniques concerning the AFC circuit are disclosed in Japanese Patent Laid-Open No. 7-297779 (hereinafter referred to as Literature 1) and Japanese Patent Laid-Open No. 8-167832 (hereinafter referred to as Literature 2), techniques concerning the demodulating system are disclosed in the Japanese Patent Laid-Open No. 3-188737 (hereinafter referred to as Literature 3), and techniques concerning automatic frequency deviation compensation are disclosed in the Japanese Patent Laid-Open No. 57-164645 (hereinafter referred to Literature 4). These literatures 1 to 4, however, disclose no means for solving the problems disclosed above.